Anti-fuse technology is popular for use in one-time programmable (OTP) memory devices and can be employed to meet various non-volatile memory requirements of many applications while offering low power operation, low cost, and excellent reliability. Known anti-fuse technologies include 2T anti-fuse bitcells and split channel 1T anti-fuse bitcells.
The 2T anti-fuse bitcells include two core N-channel metal oxide semiconductor (NMOS) transistors. For the 2T anti-fuse bitcells, a program transistor (WLP) is generally coupled in series with a select transistor (WLR), with a bitline contact connected to a source region of the select transistor. When a normal supply voltage such as an I/O or core voltage is applied to the gates of the 2T anti-fuse bitcell, no current is sensed along the bitline. The equivalent circuit for the program transistor is a capacitor. Since there is no current that flows along the bitline, the bitcell is “0” by default. When a large programming voltage is applied along the gate of the program transistor, gate oxide breakdown occurs and a resistive path is created. The equivalent circuit for the program transistor becomes a resistor. A normal supply voltage applied to the gates of the 2T anti-fuse bitcell after programming result in current flow along the bitline and a “1” is sensed. The “1”s can be programmed at any time. Once it is programmed, it cannot be reverted back to a “0”. Despite utility of the 2T anti-fuse bitcells, the two-transistor configuration is bulky and gate oxide breakdown along the gate of the program transistor is unpredictable and can occur at multiple locations. For example, gate oxide breakdown may occur in the channel of the program transistor or near the source region adjacent to the program transistor, thereby creating a bimodal distribution and raising reading error and reliability concerns.
The split channel 1T anti-fuse bitcells include a thin (core) gate and a thick (I/O) gate, with a bitline contact connected to a source region adjacent to the thick gate, with the thin gate being separated from the channel by a thinner gate dielectric layer than the thick gate. The thin gate is the program gate, while the thick gate is the select gate. When a normal supply voltage such as an I/O or core voltage is applied to the gates, no current is sensed along the bitline. The equivalent circuit is a capacitor. Since there is no current that flows along the bitline, the bitcell is “0” by default. When a large programming voltage is applied along the thin gate, a gate oxide breakdown occurs and a resistive path is created. The equivalent circuit for the thin gate is a resistor. Due to the thickness gradient, gate oxide breakdown occurs at the weakest link, which is the junction of the thick gate and thin gate. Despite enhanced controllability of gate oxide breakdown with the split cell 1T anti-fuse bitcells, the split cell 1T anti-fuse bitcells still have a large cell size and thick gate length is difficult to control during fabrication.
Accordingly, it is desirable to provide transistor devices that have an anti-fuse configuration and that are more compact than split cell 1T anti-fuse cells. Further, it is desirable to provide transistor devices that have an anti-fuse configuration and that enable gate oxide breakdown to be predictably controlled at specific locations within the transistor devices. Further still, it is desirable to provide transistor devices having an anti-fuse configuration that can be formed without the gate length control difficulties associated with split cell 1T anti-fuse bitcells. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.